1. Field of the Invention
The present invention relates to a semiconductor package substrate, a design method thereof, a manufacturing method thereof and design support apparatus thereof. More particularly, the present invention relates to a semiconductor package substrate on which a semiconductor chip is primarily mounted and which is secondly mounted on a secondary mounting substrate, and a designing method thereof, a manufacturing method thereof, and a design support apparatus for supporting the design thereof.
2. Description of Related Art
In a connection portion of a semiconductor chip and a semiconductor package substrate primarily mounting the semiconductor chip, the impedance matching between the input and output of both units is important. In an input/output pad of the semiconductor chip, 50Ω is considered to be a standard value of the input/output impedance when it is observed from the outside. Thus, an input/output impedance of the semiconductor package substrate when it is observed from the semiconductor chip is ideally designed to be equal to the standard value.
For such a design, for example, a technique for achieving the impedance matching is known in which a layout pattern formed in a printed circuit board is used. Specifically, capacitor elements can be formed by a copper foil layer which is formed other than the signal layer. By adopting this technique, the impedance matching is achieved without additional electronic parts.
In relation to the above technique, the patent document 1 (Japanese Laid-Open Patent Application JP-P2000-151115A) discloses an invention related to a printed circuit board.
The printed circuit board of the invention in the patent document 1 contains a plurality of conductive layers, interconnections and capacitor elements. Here, the plurality of conductive layers are sequentially laminated via insulating layers between them. The interconnection is formed by the conductive layer for connecting the circuit parts to be mounted to each other. The capacitor element is formed by an insulating layer and a conductive layer opposing via this insulating layer and connected to interconnections for achieving the impedance matching of circuit parts.
Also, in the patent document 2 (Japanese Laid-Open Patent Application JP-P2004-146810A), an invention regarding a printed circuit board is described. The printed circuit board of this invention contains a multilayer substrate, via holes, surface layer interconnections, at least one inner layer interconnection and conductive members. Here, the via hole is formed to pierce the multilayer substrate. The surface layer interconnection is formed on the surface layer of the multilayer substrate and connected to a first end which is an end of the via hole. At least one inner layer interconnection is formed inside the multilayer substrate and connected to a conductive portion of the via hole at a position other than the top and bottom end thereof. The conductive member is connected to a second end, being positioned on the side opposite to the first end of the conductive portion of the via hole, to which the surface layer interconnection is not connected.
The conductive member has an electrical length so that the value of the impedance at a predetermined frequency is higher than a predetermined value, when the conductive member is observed from a first connecting point which is one of the connecting points between the inner layer and the conductive portion of the via hole and closest to the second end. The predetermined value is the impedance value of the second end portion at a predetermined frequency, when it is observed from the first connecting point in a case where the conductive member does not exist.
Also, the patent document 3 (Japanese Laid-open Patent Application JP-P2005-197720A) discloses an invention regarding a multilayer substrate.
The multilayer substrate of the invention in the patent document 3 contains: a plurality of metal layers on which predetermined printed circuit patterns are respectively formed; and insulating layers respectively formed between the metal layers. Here, the plurality of metal layers contain at least two high frequency signal layers and at least one ground layer. The at least two high frequency signal layers are provided for transmitting high frequency signals. The at least one ground layer is provided for supplying the ground to the other metal layers. This multilayer substrate contains at least one via hole and an impedance matching hole. The at least one via hole is formed to pierce the multilayer substrate for connecting the high frequency signal layers to each other. The impedance matching hole is formed to pierce the ground layer for providing a path through which the via hole is arranged.
This multilayer substrate is characterized in that the separation distance between the via hole and the ground layer is suitably adjusted by the impedance matching hole to adjust the capacitance, and together with the inductance specific to the via hole, the state similar to the waveguide path is exhibited, thereby attaining the impedance matching of the multilayer substrate when high frequency signals are transmitted between the high frequency signal layers.
The patent document 4 (Japanese Laid-Open Patent Application JP-P2005-236064A) discloses an invention regarding a signal transmission pair interconnection.
The signal transmission pair interconnection of the invention in the patent document 4 is formed by laminating a plurality of patterned metal layers and a dielectric layer and connecting the layers by via holes. This signal transmission pair interconnection is characterized in that the diameter and the interval of the vias through which the plurality of interconnections formed by the patterned metal layers are connected to each other are adjusted so that the characteristic impedance becomes a constant value.